Song Peng, Rajit Manohar. Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology. In Gang Qu, Yehea I. Ismail, Narayanan Vijaykrishnan, Hai Zhou, editors, Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006. pages 159-164, ACM, 2006. [doi]
@inproceedings{PengM06:2,
title = {Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology},
author = {Song Peng and Rajit Manohar},
year = {2006},
doi = {10.1145/1127908.1127947},
url = {http://doi.acm.org/10.1145/1127908.1127947},
tags = {logic},
researchr = {https://researchr.org/publication/PengM06%3A2},
cites = {0},
citedby = {0},
pages = {159-164},
booktitle = {Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006},
editor = {Gang Qu and Yehea I. Ismail and Narayanan Vijaykrishnan and Hai Zhou},
publisher = {ACM},
isbn = {1-59593-347-6},
}