Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis

André B. Perina, Arthur Silitonga, Jürgen Becker 0001, Vanderlei Bonato. Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis. IEEE Transactions on Computers, 70(12):2070-2082, 2021. [doi]

Authors

André B. Perina

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Arthur Silitonga

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Jürgen Becker 0001

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Vanderlei Bonato

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