André B. Perina, Arthur Silitonga, Jürgen Becker 0001, Vanderlei Bonato. Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis. IEEE Transactions on Computers, 70(12):2070-2082, 2021. [doi]
@article{PerinaSBB21,
title = {Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis},
author = {André B. Perina and Arthur Silitonga and Jürgen Becker 0001 and Vanderlei Bonato},
year = {2021},
doi = {10.1109/TC.2021.3112260},
url = {https://doi.org/10.1109/TC.2021.3112260},
researchr = {https://researchr.org/publication/PerinaSBB21},
cites = {0},
citedby = {0},
journal = {IEEE Transactions on Computers},
volume = {70},
number = {12},
pages = {2070-2082},
}