A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS - researchr publication

researchr

You are not signed in
Sign in
Sign up

Dirk Pfaff, Robert Abbott, Xin-jie Wang, Shahaboddin Moazzeni, Ralph Mason, Raleigh Smith. A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS. J. Solid-State Circuits, 55(3):580-591, 2020. [doi]

Abstract is missing.

runs on WebDSL