A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET - researchr publication authors

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Dirk Pfaff, Robert Abbott, Xin-jie Wang, Babak Zamanlooy, Shahaboddin Moazzeni, Raleigh Smith, Chih-Chang Lin. A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET. In IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, TX, USA, April 14-17, 2019. pages 1-4, IEEE, 2019. [doi]

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