Dirk Pfaff, Robert Abbott, Xin-jie Wang, Babak Zamanlooy, Shahaboddin Moazzeni, Raleigh Smith, Chih-Chang Lin. A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET. In IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, TX, USA, April 14-17, 2019. pages 1-4, IEEE, 2019. [doi]
@inproceedings{PfaffAWZMSL19,
title = {A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET},
author = {Dirk Pfaff and Robert Abbott and Xin-jie Wang and Babak Zamanlooy and Shahaboddin Moazzeni and Raleigh Smith and Chih-Chang Lin},
year = {2019},
doi = {10.1109/CICC.2019.8780247},
url = {https://doi.org/10.1109/CICC.2019.8780247},
researchr = {https://researchr.org/publication/PfaffAWZMSL19},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {IEEE Custom Integrated Circuits Conference, CICC 2019, Austin, TX, USA, April 14-17, 2019},
publisher = {IEEE},
isbn = {978-1-5386-9395-7},
}