The following publications are possibly variants of this publication:
- Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois FieldsHuyen Thi Pham, Hanho Lee. tvlsi, 26(3):496-507, 2018. [doi]
- Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC CodesHuyen Thi Pham, Hanho Lee. tvlsi, 25(5):1787-1791, 2017. [doi]
- Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codesHuyen Pham Thi, Hanho Lee, Xuan Nghia Pham. integration, 69:234-241, 2019. [doi]
- An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum AlgorithmChia-Lung Lin, Shu-Wen Tu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee. tcas, 63-II(9):863-867, 2016. [doi]
- Reduced-Complexity Trellis Min-Max Decoder for Non-Binary Ldpc CodesHuyen Pham Thi, Hanho Lee. icassp 2018: 1179-1183 [doi]