Harold Pilo, Manish Arora, Chien-An Lai, Mike Lee, Zack Lo, Mayur Randeria. A 37.8 Mb/mm² SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection. IEEE Solid State Circuits Lett., 8:357-360, 2025. [doi]
@article{PiloALLLR25,
title = {A 37.8 Mb/mm² SRAM in Intel 18A Technology Featuring a Resistive Supply-Line Write Scheme and Write-Assist With Parallel Boost Injection},
author = {Harold Pilo and Manish Arora and Chien-An Lai and Mike Lee and Zack Lo and Mayur Randeria},
year = {2025},
doi = {10.1109/LSSC.2025.3628176},
url = {https://doi.org/10.1109/LSSC.2025.3628176},
researchr = {https://researchr.org/publication/PiloALLLR25},
cites = {0},
citedby = {0},
journal = {IEEE Solid State Circuits Lett.},
volume = {8},
pages = {357-360},
}