Irith Pomeranz, Sudhakar M. Reddy. Reducing test application time for full scan circuits by the addition of transfer sequences. In 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan. pages 317-322, IEEE Computer Society, 2000. [doi]
@inproceedings{PomeranzR00a:0, title = {Reducing test application time for full scan circuits by the addition of transfer sequences}, author = {Irith Pomeranz and Sudhakar M. Reddy}, year = {2000}, url = {http://csdl.computer.org/comp/proceedings/ats/2000/0887/00/08870317abs.htm}, tags = {testing}, researchr = {https://researchr.org/publication/PomeranzR00a%3A0}, cites = {0}, citedby = {0}, pages = {317-322}, booktitle = {9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan}, publisher = {IEEE Computer Society}, isbn = {0-7695-0887-1}, }