Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits

Irith Pomeranz, Sudhakar M. Reddy. Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits. Journal of Systems Architecture, 47(3-4):357-373, 2001. [doi]

Authors

Irith Pomeranz

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Sudhakar M. Reddy

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