Irith Pomeranz, Sudhakar M. Reddy. Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. In VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010. pages 39-44, IEEE, 2010. [doi]
@inproceedings{PomeranzR10a, title = {Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration}, author = {Irith Pomeranz and Sudhakar M. Reddy}, year = {2010}, doi = {10.1109/VLSI.Design.2010.16}, url = {http://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2010.16}, tags = {testing, logic}, researchr = {https://researchr.org/publication/PomeranzR10a}, cites = {0}, citedby = {0}, pages = {39-44}, booktitle = {VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010}, publisher = {IEEE}, isbn = {978-0-7695-3928-7}, }