Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling

Irith Pomeranz, Sudhakar M. Reddy. Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling. In 8th Great Lakes Symposium on VLSI (GLS-VLSI 98), 19-21 February 1998, Lafayette, LA, USA. pages 216-221, IEEE Computer Society, 1998. [doi]

Authors

Irith Pomeranz

This author has not been identified. Look up 'Irith Pomeranz' in Google

Sudhakar M. Reddy

This author has not been identified. Look up 'Sudhakar M. Reddy' in Google