Post-Synthesis Circuit Techniques for Runtime Leakage Reduction

Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti. Post-Synthesis Circuit Techniques for Runtime Leakage Reduction. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India. pages 319-320, IEEE Computer Society, 2011. [doi]

@inproceedings{PotluriCK11,
  title = {Post-Synthesis Circuit Techniques for Runtime Leakage Reduction},
  author = {Seetal Potluri and Nitin Chandrachoodan and V. Kamakoti},
  year = {2011},
  doi = {10.1109/ISVLSI.2011.24},
  url = {http://dx.doi.org/10.1109/ISVLSI.2011.24},
  researchr = {https://researchr.org/publication/PotluriCK11},
  cites = {0},
  citedby = {0},
  pages = {319-320},
  booktitle = {IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India},
  publisher = {IEEE Computer Society},
}