Dhiraj K. Pradhan, Jayashree Saxena. A design for testability scheme to reduce test application time in full scan. In 10th IEEE VLSI Test Symposium (VTS'92), 7-9 Apr 1992, Atlantic City, NJ, USA. pages 55-60, IEEE, 1992. [doi]
@inproceedings{PradhanS92,
title = {A design for testability scheme to reduce test application time in full scan},
author = {Dhiraj K. Pradhan and Jayashree Saxena},
year = {1992},
doi = {10.1109/VTEST.1992.232724},
url = {http://dx.doi.org/10.1109/VTEST.1992.232724},
researchr = {https://researchr.org/publication/PradhanS92},
cites = {0},
citedby = {0},
pages = {55-60},
booktitle = {10th IEEE VLSI Test Symposium (VTS'92), 7-9 Apr 1992, Atlantic City, NJ, USA},
publisher = {IEEE},
isbn = {0-7803-0623-6},
}