Researchr is a web site for finding, collecting, sharing, and reviewing scientific publications, for researchers by researchers.
Sign up for an account to create a profile with publication list, tag and review your related work, and share bibliographies with your co-authors.
Dhiraj K. Pradhan, Jayashree Saxena. A design for testability scheme to reduce test application time in full scan. In 10th IEEE VLSI Test Symposium (VTS'92), 7-9 Apr 1992, Atlantic City, NJ, USA. pages 55-60, IEEE, 1992. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A novel scheme to reduce test application time in circuits with full scanDhiraj K. Pradhan, Jayashree Saxena. tcad, 14(12):1577-1586, 1995. [doi]
The following publications are possibly variants of this publication: