A design for testability scheme to reduce test application time in full scan

Dhiraj K. Pradhan, Jayashree Saxena. A design for testability scheme to reduce test application time in full scan. In 10th IEEE VLSI Test Symposium (VTS'92), 7-9 Apr 1992, Atlantic City, NJ, USA. pages 55-60, IEEE, 1992. [doi]

Abstract

Abstract is missing.