A novel scheme to reduce test application time in circuits with full scan

Dhiraj K. Pradhan, Jayashree Saxena. A novel scheme to reduce test application time in circuits with full scan. IEEE Trans. on CAD of Integrated Circuits and Systems, 14(12):1577-1586, 1995. [doi]

Authors

Dhiraj K. Pradhan

This author has not been identified. Look up 'Dhiraj K. Pradhan' in Google

Jayashree Saxena

This author has not been identified. Look up 'Jayashree Saxena' in Google