Dhiraj K. Pradhan, Jayashree Saxena. A novel scheme to reduce test application time in circuits with full scan. IEEE Trans. on CAD of Integrated Circuits and Systems, 14(12):1577-1586, 1995. [doi]
@article{PradhanS95,
title = {A novel scheme to reduce test application time in circuits with full scan},
author = {Dhiraj K. Pradhan and Jayashree Saxena},
year = {1995},
doi = {10.1109/43.476587},
url = {http://doi.ieeecomputersociety.org/10.1109/43.476587},
tags = {testing},
researchr = {https://researchr.org/publication/PradhanS95},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {14},
number = {12},
pages = {1577-1586},
}