Operation-aware assist circuit design for improved write performance of FinFET based SRAM

Ekta Prajapati, Nandakishor Yadav, Manisha Pattanaik, G. K. Sharma. Operation-aware assist circuit design for improved write performance of FinFET based SRAM. In 18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, India, July 16-18, 2014. pages 1-6, IEEE, 2014. [doi]

@inproceedings{PrajapatiYPS14,
  title = {Operation-aware assist circuit design for improved write performance of FinFET based SRAM},
  author = {Ekta Prajapati and Nandakishor Yadav and Manisha Pattanaik and G. K. Sharma},
  year = {2014},
  doi = {10.1109/ISVDAT.2014.6881063},
  url = {http://dx.doi.org/10.1109/ISVDAT.2014.6881063},
  researchr = {https://researchr.org/publication/PrajapatiYPS14},
  cites = {0},
  citedby = {0},
  pages = {1-6},
  booktitle = {18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, India, July 16-18, 2014},
  publisher = {IEEE},
  isbn = {978-1-4799-5088-1},
}