Abstract is missing.
- Power analysis attack using neural networks with wavelet transform as pre-processorP. Saravanan, P. Kalpana, V. Prcethisri, V. Sneha. 1-6 [doi]
- Layout-aware signal selection in reconfigurable architecturesPrateek Thakyal, Prabhat Mishra. 1-6 [doi]
- An approach for efficient FIR filter design for hearing aid applicationSrinivasa Reddy Kotha, Devendra Bilaye, Utkarsh Jain, Sahoo Subhendu Kumar. 1-5 [doi]
- Automatic real-time extraction of focused regions in a live video stream using edge width informationSanjay Singh, Sumeet Saurav, Ravi Saini, Anil K. Saini, Chandra Shekhar, Anil Vohra. 1-2 [doi]
- An ultra low power MICS/ISM band transmitter in 0.18 μm CMOSAmitava Ghosh, Anindya Sundar Dhar, Achintya Halder. 1-6 [doi]
- A re-router for optimizing wire length in two-and four-layer no-dogleg channel routingSwagata Saha Sau, Rajat Kumar Pal. 1-6 [doi]
- A positive level shifter for high speed symmetric switching in flash memoriesRohan Sinha, M. S. Hashmi, G. Anil Kumar. 1-5 [doi]
- Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power applicationM. Chanda, A. S. Chakraborty, S. Nag, R. Modak. 1-2 [doi]
- Signature analysis for synthesis of reversible circuitPalash Das, Bikromadittya Mondal. 1-2 [doi]
- Cryptanalysis of Composite PUFs (Extended abstract-invited talk)Phuong Ha Nguyen, Durga Prasad Sahoo, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty. 1-2 [doi]
- Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solversKunal Banerjee, Chittaranjan A. Mandal, Dipankar Sarkar. 1-6 [doi]
- Distributed adaptive routing for spidergon NoCRimpy Bishnoi, Pankaj Kumar Srivastava, Vijay Laxmi, Manoj Singh Gaur, Apoorva Sikka. 1-6 [doi]
- TID effects on retention of 0.13 μm SONOS memory cell: A device simulation approachShipra Bassi, Manisha Pattanaik. 1-6 [doi]
- Design of a new high order OTA-C filter structure and its specification based testingK. Ghosh, B. N. Ray. 1-6 [doi]
- Design and modeling of high-Q variable width and spacing, planar and 3-D stacked spiral inductorsR. R. Manikandan, Venkata Narayana Rao Vanukuru, Anjan Chakravorty, Bharadwaj S. Amrutur. 1-6 [doi]
- Artificial neural network modelling of ADS designed Double Pole Double Throw switchShubhankar Majumdar, Mohd. Zuhair, Dhrubes Biswas. 1-2 [doi]
- FPGA-based real-time object tracker using modified particle filtering and SAD computationSanjay Singh, Ravi Saini, Sumeet Saurav, Anil K. Saini, Chandra Shekhar, Anil Vohra. 1-2 [doi]
- FPGA-based implementation of M4RM for matrix multiplication over GF(2)Vivek Kumar, Vinay B. Y. Kumar, Sachin B. Patkar. 1-2 [doi]
- A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-ChipNarendra Kumar Meena, Hemangee K. Kapoor, Shounak Chakraborty. 1-6 [doi]
- A thermal aware 3D IC partitioning techniqueSabyasachee Banerjee, Subhashis Majumder. 1-6 [doi]
- An LUT based RNS FIR filter implementation for reconfigurable applicationsSrinivasa Reddy Kotha, Sumit Bajaj, Sahoo Subhendu Kumar. 1-6 [doi]
- Loop unrolling with fine grained power gating for runtime leakage power reductionSumanta Pyne, Ajit Pal. 1-6 [doi]
- A Pseudo-Deadline Based O(1) proportional share scheduler for embedded systemsSwarnendu Ray, Arnab Sarkar. 1-2 [doi]
- Deterministic seed selection and pattern reduction in Logic BISTRamesh Bhakthavatchalu, Sreeja Krishnan, V. Vineeth, M. Nirmala Devi. 1-2 [doi]
- Design of a fault tolerant low-order interleaved memory based on the concept of bubble-stack an image storage perspectiveSomak Das, Sowvik Dey. 1-6 [doi]
- A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applicationsIndrajit Das, Manodipan Sahoo, Pranab Roy, Hafizur Rahaman. 1-6 [doi]
- VLSI design of fast fractal image encoderMamata Panigrahy, Indrajit Chakrabarti, Anindya Sundar Dhar. 1-2 [doi]
- Study of reverse substrate bias effect of 22nm node epitaxial delta doped channel MOS transistor for low power SoC applicationsDebayan Bairagi, Soumya Pandit. 1-6 [doi]
- A locally reconfigurable Network-on-Chip architecture and application mapping onto itSoumya J., Ashish Sharma, Santanu Chattopadhyay. 1-6 [doi]
- Architectures and algorithms for image and video processing using FPGA-based platformJ. G. Pandey, Arindam Karmakar, S. Gurunarayanan. 1 [doi]
- Tunnel FET based low voltage static vs dynamic logic families for energy efficiencyKasturi Subramanyam, Sadulla Shaik, Ramesh Vaddi. 1-2 [doi]
- All optical implementation of Mach-Zehnder interferometer based reversible sequential circuitPratik Dutta, Chandan Bandyopadhyay, Hafizur Rahaman. 1-2 [doi]
- An analytical delay model for CMOS Inverter-Transmission Gate structureMohammad Shueb Romi, Naushad Alam, Mohd Yusuf Yasin. 1-6 [doi]
- Particle Swarm Optimization guided multi-frequency power-aware System-on-Chip test scheduling using window-based peak power modelRajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay. 1-6 [doi]
- Hardware accelerator for real-time image resizingPranav Narayan Gour, Sujay Narumanchi, Sumeet Saurav, Sanjay Singh. 1-6 [doi]
- VLSI implementation of novel fast confluence ICA algorithm for signal processing applicationsM. E. Jayasanthi Ranjith, N. J. R. Muniraj. 1-2 [doi]
- Modelling and analysis of wireless communication over Networks-on-ChipApoorv Kumar, Hemangee K. Kapoor. 1-6 [doi]
- A 32×32 CMOS image sensor: Tested using process and temperature compensated voltage controlled current sourceP. Saidesh Kumar, M. A. Seenivasan. 1-6 [doi]
- Operation-aware assist circuit design for improved write performance of FinFET based SRAMEkta Prajapati, Nandakishor Yadav, Manisha Pattanaik, G. K. Sharma. 1-6 [doi]
- An analytic potential and threshold voltage model for short-channel symmetric double-gate MOSFETVimal Kumar Singh Yadav, Ratul Kr. Baruah. 1-2 [doi]
- An FPGA implementation of image signature based visual-saliency detectionBhavit Kaushik, Ravi Saini, Anil K. Saini, Sanjay Singh, A. S. Mandal. 1-6 [doi]
- Design of tunnel FET based low power digital circuitsAkhila Kamal, B. Bindu. 1-2 [doi]
- Timing-driven Steiner tree construction on uniform λ-geometryRadhamanjari Samanta, Adil I. Erzin, Soumyendu Raha. 1-4 [doi]
- A spare link based reliable Network-on-Chip designNavonil Chatterjee, N. Prasad, Santanu Chattopadhyay. 1-6 [doi]
- UVM based STBUS verification IP for verifying SoC architecturesPranay Samanta, Deepak Chauhan, Sujay Deb, Piyush Kumar Gupta. 1-2 [doi]
- High permittivity spacer effects on junctionless FinFET based circuit/SRAM applicationsDilsukh Nehra, Pankaj Kumar Pal, B. K. Kaushik, S. DasGupta. 1-6 [doi]
- An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity EffectBijay Kumar Dalai, N. Karnnan, Arvind Sharma, Bulusu Anand. 1-2 [doi]
- Power optimized PLL implementation in 180nm CMOS technologyPatri Sreehari, Pavankumarsharma Devulapalli, Dhananjay Kewale, Omkar Asbe, K. S. R. Krishna Prasad. 1-2 [doi]
- A regular network of symmetric functions in quantum-dot cellular automataArighna Deb, Debesh Kumar Das. 1-6 [doi]
- 250mA ultra low drop out regulator with high slew rate double recycling folded cascode error amplifierSreehari Rao Patri, Suresh Alapati, Surendra Chowdary, K. S. R. Krishna Prasad. 1-5 [doi]
- An efficient hardware architecture for stereo disparity estimationFradaric Joseph, Kiran Francis, Archita Hore, Siddhanta Roy, S. Josephine, Roy P. Paily. 1-6 [doi]
- Modeling and simulation of variable thickness based stepped MEMS cantilever designs for biosensing and pull-in voltage optimizationDeep Kishore Parsediya, Jawar Singh, Pavan Kumar Kankar. 1-2 [doi]
- Pipelined FFT architectures for real-time signal processing and wireless communication applicationsAntony Xavier Glittas, G. Lakshminarayanan. 1-2 [doi]
- A BDD based secure hardware design method to guard against power analysis attacksPartha De, Kunal Banerjee, Chittaranjan A. Mandal. 1-2 [doi]
- A novel architecture for QPSK modulation based on time-mode signal processingSumit Saha, Bapi Kar, Susmita Sur-Kolay. 1-6 [doi]