Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors

Abhijit Prasad, D. M. H. Walker. Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors. In 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings. pages 140, IEEE Computer Society, 2003. [doi]

@inproceedings{PrasadW03,
  title = {Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors},
  author = {Abhijit Prasad and D. M. H. Walker},
  year = {2003},
  url = {http://csdl.computer.org/comp/proceedings/dft/2003/2042/00/20420140abs.htm},
  tags = {testing, partitioning},
  researchr = {https://researchr.org/publication/PrasadW03},
  cites = {0},
  citedby = {0},
  pages = {140},
  booktitle = {18th  IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-2042-1},
}