V. Prasanth, Virendra Singh, Rubin A. Parekhji. Derating based hardware optimizations in soft error tolerant designs. In 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012. pages 282-287, IEEE, 2012. [doi]
@inproceedings{PrasanthSP12, title = {Derating based hardware optimizations in soft error tolerant designs}, author = {V. Prasanth and Virendra Singh and Rubin A. Parekhji}, year = {2012}, doi = {10.1109/VTS.2012.6231067}, url = {http://dx.doi.org/10.1109/VTS.2012.6231067}, researchr = {https://researchr.org/publication/PrasanthSP12}, cites = {0}, citedby = {0}, pages = {282-287}, booktitle = {30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012}, publisher = {IEEE}, isbn = {978-1-4673-1074-1}, }