Derating based hardware optimizations in soft error tolerant designs

V. Prasanth, Virendra Singh, Rubin A. Parekhji. Derating based hardware optimizations in soft error tolerant designs. In 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012. pages 282-287, IEEE, 2012. [doi]

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