A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next-Generation Memory Interfaces

E. Prete, D. Scheideler, A. Sanders. A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next-Generation Memory Interfaces. In 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006. pages 253-262, IEEE, 2006. [doi]

@inproceedings{PreteSS06,
  title = {A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next-Generation Memory Interfaces},
  author = {E. Prete and D. Scheideler and A. Sanders},
  year = {2006},
  doi = {10.1109/ISSCC.2006.1696055},
  url = {https://doi.org/10.1109/ISSCC.2006.1696055},
  researchr = {https://researchr.org/publication/PreteSS06},
  cites = {0},
  citedby = {0},
  pages = {253-262},
  booktitle = {2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006},
  publisher = {IEEE},
  isbn = {1-4244-0079-1},
}