Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper) - researchr publication authors

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Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu. Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). In 2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, CA, USA, November 13-16, 2017. pages 929-936, IEEE, 2017. [doi]

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