Table of Contents

• Leveraging value locality for efficient design of a hybrid cache in multicore processorsMohammad Arjomand, Amin Jadidi, Mahmut T. Kandemir, Chita R. Das. 1-8 [doi]
• Keynote addresses: Quantum computing: Revolutionizing computation through quantum mechanicsKrysta M. Svore. 1-2 [doi]
• Front-end-of-line attacks in split manufacturingYujie Wang, Tri Cao, Jiang Hu, Jeyavijayan Rajendran. 1-8 [doi]
• Energy-efficient and robust 3D NoCs with contactless vertical links (Invited paper)Sourav Das, Srinivasan Gopal, Deukhyoun Heo, Partha Pratim Pande. 1-6 [doi]
• Exploring cache bypassing and partitioning for multi-tasking on GPUsYun Liang 0001, Xiuhong Li, Xiaolong Xie. 9-16 [doi]
• Virtual persistent cache: Remedy the long latency behavior of host-aware shingled magnetic recording drivesMing-Chang Yang, Yuan-Hao Chang, Fenggang Wu, Tei-Wei Kuo, David H. C. Du. 17-24 [doi]
• ORCHARD: Visual object recognition accelerator based on approximate in-memory processingYeseong Kim, Mohsen Imani, Tajana Rosing. 25-32 [doi]
• Reverse engineering camouflaged sequential circuits without scan accessMohamed El Massad, Siddharth Garg, Mahesh Tripunitara. 33-40 [doi]
• Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflagingSatwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu. 41-48 [doi]
• CycSAT: SAT-based attack on cyclic logic encryptionsHai Zhou, Ruifeng Jiang, Shuyu Kong. 49-56 [doi]
• Threshold-based obfuscated keys with quantifiable security against invasive readoutShahrzad Keshavarz, Daniel Holcomb. 57-64 [doi]
• Mixed-cell-height detailed placement considering complex minimum-implant-area constraintsYen-Yi Wu, Yao-Wen Chang. 65-72 [doi]
• Blockage-aware terminal propagation for placement wirelength minimizationSheng-Wei Yang, Yao-Wen Chang, Tung-Chieh Chen. 73-80 [doi]
• A unified framework for simultaneous layout decomposition and mask optimizationYuzhe Ma, Jhih-Rong Gao, Jian Kuang 0001, Jin Miao, Bei Yu. 81-88 [doi]
• IR-drop aware Design & technology co-optimization for N5 node with different device and cell height optionsLuca Mattii, Dragomir Milojevic, Peter Debacker, Yasser Sherazi, Mladen Berekovic, Praveen Raghavan. 89-94 [doi]
• Safety model checking with complementary approximationsJianwen Li, Shufang Zhu, Yueling Zhang, Geguang Pu, Moshe Y. Vardi. 95-100 [doi]
• An automated SAT-based method for the design of on-chip bit-flip detectorsPouya Taatizadeh, Nicola Nicolici. 101-108 [doi]
• Sequential engineering change order under retiming and resynthesisNian-Ze Lee, Victor N. Kravets, Jie-Hong R. Jiang. 109-116 [doi]
• Accelerating functional timing analysis with encoding duplication removal and redundant state propagationDenny C.-Y. Wu, Pin-Ru Jhao, Charles H.-P. Wen. 117-122 [doi]
• Efficient simulation of EM side-channel attack resilienceAmit Kumar, Cody Scarborough, Ali Yilmaz, Michael Orshansky. 123-130 [doi]
• Fault injection attack on deep neural networkYannan Liu, Lingxiao Wei, Bo Luo, Qiang Xu. 131-138 [doi]
• A novel cache bank timing attackZhen Hang Jiang, Yunsi Fei. 139-146 [doi]
• Clepsydra: Modeling timing flows in hardware designsArmaiti Ardeshiricham, Wei Hu, Ryan Kastner. 147-154 [doi]
• DAGSENS: Directed acyclic graph based direct and adjoint transient sensitivity analysis for event-driven objective functionsKarthik V. Aadithya, Eric R. Keiter, Ting Mei. 155-162 [doi]
• Exploring the exponential integrators with Krylov subspace algorithms for nonlinear circuit simulationXinyuan Wang, Hao Zhuang, Chung-Kuan Cheng. 163-168 [doi]
• Fast physics-based electromigration analysis for multi-branch interconnect treesXiaoyi Wang, Yan Yan, Jian He, Sheldon X.-D. Tan, Chase Cook, Shengqi Yang. 169-176 [doi]
• Online message delay prediction for model predictive control over controller area networkAmith Kaushal Rao, Haibo Zeng. 177-184 [doi]
• Hybrid state machine model for fast model predictive control: Application to path trackingMaral Amir, Tony Givargis. 185-192 [doi]
• ACQUA: Adaptive and cooperative quality-aware control for automotive cyber-physical systemsKorosh Vatanparvar, Mohammad Abdullah Al Faruque. 193-200 [doi]
• Cross-program design space exploration by ensemble transfer learningDandan Li, Shuzhen Yao, Senzhang Wang, Ying Wang. 201-208 [doi]
• Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformationsAdam M. Izraelevitz, Jack Koenig, Patrick Li, Richard Lin, Angie Wang, Albert Magyar, Donggyu Kim, Colin Schmidt, Chick Markley, Jim Lawson, Jonathan Bachrach. 209-216 [doi]
• A load balancing inspired optimization framework for exascale multicore systems: A complex networks approachYao Xiao, Yuankun Xue, Shahin Nazarian, Paul Bogdan. 217-224 [doi]
• Simple magic: Synthesis and in-memory Mapping of logic execution for memristor-aided logicRotem Ben Hur, Nimrod Wald, Nishil Talati, Shahar Kvatinsky. 225-232 [doi]
• Dedicated synthesis for MZI-based optical circuits based on AND-inverter graphsArighna Deb, Robert Wille, Rolf Drechsler. 233-238 [doi]
• Simultaneous template assignment and layout decomposition using multiple bcp materials in DSA-MP lithographyKuo-Hao Wu, Shao-Yun Fang. 239-244 [doi]
• PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memoryLiang Chang, Zhaohao Wang, Alvin Oliver Glova, Jishen Zhao, Youguang Zhang, Yuan Xie 0001, Weisheng Zhao. 245-252 [doi]
• Cost-effective write disturbance mitigation techniques for advancing PCM densityMohammad Khavari Tavana, David R. Kaeli. 253-260 [doi]
• Speeding up crossbar resistive memory by exploiting in-memory data patternsWen Wen, Lei Zhao, Youtao Zhang, Jun Yang. 261-267 [doi]
• Approximate image storage with multi-level cell STT-MRAM main memoryHengyu Zhao, Linuo Xue, Ping Chi, Jishen Zhao. 268-275 [doi]
• A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptographyTao Luo, Bingsheng He, Wei Zhang 0012, Douglas L. Maskell. 276-282 [doi]
• VST: A virtual stress testing framework for discovering bugs in SSD flash-translation layersRen-Shuo Liu, Yun-Sheng Chang, Chih-Wen Hung. 283-290 [doi]
• AdaLearner: An adaptive distributed mobile learning system for neural networksJiachen Mao, Zhuwei Qin, Zirui Xu, Kent W. Nixon, Xiang Chen, Hai Li, Yiran Chen. 291-296 [doi]
• NEMESIS: A software approach for computing in presence of soft errorsMoslem Didehban, Aviral Shrivastava, Sai Ram Dheeraj Lokam. 297-304 [doi]
• An open benchmark implementation for multi-CPU multi-GPU pedestrian detection in automotive systemsMatina Maria Trompouki, Leonidas Kosmidis, Nacho Navarro. 305-312 [doi]
• Making split fabrication synergistically secure and manufacturableLang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran. 313-320 [doi]
• Making split fabrication synergistically secure and manufacturableLang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran. 321-328 [doi]
• Rethinking split manufacturing: An information-theoretic approach with secure layout techniquesAbhrajit Sengupta, Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Siddharth Garg, Ozgur Sinanoglu. 329-326 [doi]
• Rapid gate sizing with fewer iterations of Lagrangian RelaxationAnkur Sharma, David Chinnery, Shrirang Dhamdhere, Chris Chu. 337-343 [doi]
• Statistically certified approximate logic synthesisGai Liu, Zhiru Zhang. 344-351 [doi]
• Enabling exact delay synthesisLuca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli. 352-359 [doi]
• Learn-on-the-go: Autonomous cross-subject context learning for internet-of-things applicationsRamin Fallahzadeh, Parastoo Alinia, Hassan Ghasemzadeh. 360-367 [doi]
• Near-optimal energy allocation for self-powered wearable systemsGanapati Bhat, Jaehyun Park, Ümit Y. Ogras. 368-375 [doi]
• Optimal checkpointing for secure intermittently-powered IoT devicesZahra Ghodsi, Siddharth Garg, Ramesh Karri. 376-383 [doi]
• ATRIUM: Runtime attestation resilient under memory attacksShaza Zeitouni, Ghada Dessouky, Orlando Arias, Dean Sullivan, Ahmad Ibrahim 0002, Yier Jin, Ahmad-Reza Sadeghi. 384-391 [doi]
• Hardening extended memory access control schemes with self-verified address spacesJesse Elwell, Dmitry Evtyushkin, Dmitry Ponomarev, Nael B. Abu-Ghazaleh, Ryan Riley. 392-399 [doi]
• Early SoC security validation by VP-based static information flow analysisMuhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler. 400-407 [doi]
• Data path optimisation and delay matching for asynchronous bundled-data balsa circuitsNorman Kluge, Ralf Wollowski. 408-415 [doi]
• Approximating complex arithmetic circuits with formal error guarantees: 32-bit multipliers accomplishedMilan Ceska, Jiri Matyas, Vojtech Mrazek, Lukás Sekanina, Zdenek Vasícek, Tomás Vojnar. 416-423 [doi]
• Advanced datapath synthesis using graph isomorphismCunxi Yu, Mihir Choudhury, Andrew Sullivan, Maciej J. Ciesielski. 424-429 [doi]
• COMBA: A comprehensive model-based analysis framework for high level synthesis of real applicationsJieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He. 430-437 [doi]
• ApproxLUT: A novel approximate lookup table-based acceleratorYe Tian, Ting Wang, Qian Zhang, Qiang Xu. 438-443 [doi]
• Energy efficient runtime approximate computing on data flow graphsMingze Gao, Gang Qu. 444-449 [doi]
• MT-spike: A multilayer time-based spiking neuromorphic architecture with temporal error backpropagationTao Liu, Zihao Liu, Fuhong Lin, Yier Jin, Gang Quan, Wujie Wen. 450-457 [doi]
• Energy-efficient, high-performance, highly-compressed deep neural network design using block-circulant matricesSiyu Liao, Zhe Li 0001, Xue Lin, Qinru Qiu, Yanzhi Wang, Bo Yuan. 458-465 [doi]
• Power scheduling with active power gridsZahi Moudallal, Farid N. Najm. 466-473 [doi]
• Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCsBi-Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Ying Wang, Weisheng Zhao. 474-481 [doi]
• Thermal modeling and design on smartphones with heat pipe cooling techniqueHong-Wen Chiou, Yu-Min Lee, Hsuan-Hsuan Hsiao, Liang-Chia Cheng. 482-489 [doi]
• Computationally efficient standard-cell FEM-based thermal analysisYi-Chung Chen, Scott Ladenheim, Harry Kalargaris, Milan Mihajlovic, Vasilis F. Pavlidis. 490-495 [doi]
• An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designsSzu-To Chen, Yao-Wen Chang, Tung-Chieh Chen. 496-503 [doi]
• A novel damped-wave framework for macro placementChin-Hao Chang, Yao-Wen Chang, Tung-Chieh Chen. 504-511 [doi]
• GRASP based metaheuristics for layout pattern classificationMingyu Woo, Seungwon Kim, Seokhyeong Kang. 512-518 [doi]
• Clock-aware placement for large-scale heterogeneous FPGAsYun-Chih Kuo, Chau-Chin Huang, Shih-Chun Chen, Chun-Han Chiang, Yao-Wen Chang, Sy-Yen Kuo. 519-526 [doi]
• RRAM-based reconfigurable in-memory computing architecture with hybrid routingYue Zha, Jing Li. 527-532 [doi]
• TraNNsformer: Neural network transformation for memristive crossbar based neuromorphic system designAayush Ankit, Abhronil Sengupta, Kaushik Roy 0001. 533-540 [doi]
• A closed-loop design to enhance weight stability of memristor based neural network chipsBonan Yan, Jianhua Yang, Qing Wu, Yiran Chen, Hai Li. 541-548 [doi]
• Memristor-based perceptron classifier: Increasing complexity and coping with imperfect hardwareFarnood Merrikh-Bayat, Mirko Prezioso, Bhaswar Chakrabarti, Irina Kataeva, Dmitri B. Strukov. 549-554 [doi]
• Switch cell optimization of power-gated modern system-on-chipsDongyoun Yi, Taewhan Kim. 555-560 [doi]
• Redistribution layer routing for wafer-level integrated fan-out package-on-packagesTing-Chou Lin, Chia-Chih Chi, Yao-Wen Chang. 561-568 [doi]
• SALT: Provably good routing topology by a novel steiner shallow-light tree algorithmGengjie Chen, Peishan Tu, Evangeline F. Y. Young. 569-576 [doi]
• A coordinated synchronous and asynchronous parallel routing approach for FPGAsMinghua Shen, Guojie Luo, Nong Xiao. 577-584 [doi]
• Scalable N-worst algorithms for dynamic timing and activity analysisHari Cherupalli, John Sartori. 585-592 [doi]
• Power grid verification under transient constraintsMohammad Fawaz, Farid N. Najm. 593-600 [doi]
• SAMG: Sparsified graph-theoretic algebraic multigrid for solving large symmetric diagonally dominant (SDD) matricesZhiqiang Zhao, Yongyu Wang, Zhuo Feng. 601-606 [doi]
• State retention for power gated design with non-uniform multi-bit retention latchesGuo-Gin Fan, Mark Po-Hung Lin. 607-614 [doi]
• Adaptive error recovery in MEDA biochips based on droplet-aliquot operations and predictive analysisZhanwei Zhong, Zipeng Li, Krishnendu Chakrabarty. 615-622 [doi]
• Sortex: Efficient timing-driven synthesis of reconfigurable flow-based biochips for scalable single-cell screeningMohamed Ibrahim, Aditya Sridhar, Krishnendu Chakrabarty, Ulf Schlichtmann. 623-630 [doi]
• A spike-based long short-term memory on a neurosynaptic processorAmar Shrestha, Khadeer Ahmed, Yanzhi Wang, David P. Widemann, Adam T. Moody, Brian C. Van Essen, Qinru Qiu. 631-637 [doi]
• Design of accurate stochastic number generators with noisy emerging devices for stochastic computingMeng Yang, John P. Hayes, Deliang Fan, Weikang Qian. 638-644 [doi]
• Stress-aware performance evaluation of 3D-stacked wide I/O DRAMsTengtao Li, Sachin S. Sapatnekar. 645-650 [doi]
• Dynamic partitioning to mitigate stuck-at faults in emerging memoriesJiangwei Zhang, Donald Kline Jr., Liang Fang, Rami G. Melhem, Alex K. Jones. 651-658 [doi]
• Fast physics-based electromigration assessment by efficient solution of linear time-invariant (LTI) systemsSandeep Chatterjee, Valeriy Sukharev, Farid N. Najm. 659-666 [doi]
• Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSIChangHo Han, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang, Bangqi Xu. 667-674 [doi]
• SAT-based compilation to a non-vonNeumann processorSamit Chaudhuri, Asmus Hetzel. 675-682 [doi]
• 4: Phase-based power/performance prediction of heterogeneous systems via neural networksYeseong Kim, Pietro Mercati, Ankit More, Emily Shriver, Tajana Rosing. 683-690 [doi]
• HLScope+, : Fast and accurate performance estimation for FPGA HLSYoung Kyu Choi, Peng Zhang, Peng Li, Jason Cong. 691-698 [doi]
• A streaming clustering approach using a heterogeneous system for big data analysisDajung Lee, Alric Althoff, Dustin Richmond, Ryan Kastner. 699-706 [doi]
• Why you should care about don't cares: Exploiting internal don't care conditions for hardware TrojansWei Hu, Lu Zhang, Armaiti Ardeshiricham, Jeremy Blackstone, Bochuan Hou, Yu Tai, Ryan Kastner. 707-713 [doi]
• Mining mutation testing simulation traces for security and testbench debuggingNicole Fern, Kwang-Ting Cheng. 714-721 [doi]
• ACE: Adaptive channel estimation for detecting analog/RF trojans in WLAN transceiversKiruba Sankaran Subramani, Angelos Antonopoulos, Ahmed Attia Abotabl, Aria Nosratinia, Yiorgos Makris. 722-727 [doi]
• Cost-effective design of scalable high-performance systems using active and passive interposersDylan Stow, Yuan Xie 0001, Taniya Siddiqua, Gabriel H. Loh. 728-735 [doi]
• Towards warp-scheduler friendly STT-RAM/SRAM hybrid GPGPU register file designQuan Deng, Youtao Zhang, Minxuan Zhang, Jun Yang. 736-742 [doi]
• A case for low frequency single cycle multi hop NoCs for energy efficiency and high performanceMonodeep Kar, Tushar Krishna. 743-750 [doi]
• MeDNN: A distributed mobile system with enhanced partition and deployment for large-scale DNNsJiachen Mao, Zhongda Yang, Wei Wen, Chunpeng Wu, Linghao Song, Kent W. Nixon, Xiang Chen, Hai Li, Yiran Chen. 751-756 [doi]
• DtCraft: A distributed execution engine for compute-intensive applicationsTsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong. 757-765 [doi]
• AEP: An error-bearing neural network accelerator for energy efficiency and model protectionLei Zhao, Youtao Zhang, Jun Yang. 765-771 [doi]
• Efficient programming of reconfigurable radio frequency (RF) systemsMohamed Baker Alawieh, Fa Wang, Jun Tao, Shihui Yin, Minhee Jun, Xin Li, Tamal Mukherjee, Rohit Negi. 772-779 [doi]
• Towards reliability-aware circuit design in nanoscale FinFET technology: - New-generation aging model and circuit reliability simulatorShaofeng Guo, Runsheng Wang, Zhuoqing Yu, Peng Hao, Pengpeng Ren, Yangyuan Wang, Siyu Liao, Chunyi Huang, Tianlei Guo, Alvin Chen, Jushan Xie, Ru Huang. 780-785 [doi]
• Online and incremental machine learning approaches for IC yield improvementHongge Chen, Duane S. Boning. 786-793 [doi]
• An analog SAT solver based on a deterministic dynamical system: (Invited paper)Xunzhao Yin, Zoltán Toroczkai, Xiaobo Sharon Hu. 794-799 [doi]
• Connecting spectral techniques for graph coloring and eigen properties of coupled dynamics: A pathway for solving combinatorial optimizations (Invited paper)Abhinav Parihar, Nikhil Shukla, Matthew Jerry, Suman Datta, Arijit Raychowdhury. 800-804 [doi]
• Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper)Kyungwook Chang, Abhishek Koneru, Krishnendu Chakrabarty, Sung Kyu Lim. 805-810 [doi]
• Leveraging recovery effect to reduce electromigration degradation in power/ground TSVShengcheng Wang, Zeyu Sun, Yuan Cheng, Sheldon X.-D. Tan, Mehdi Baradaran Tahoori. 811-818 [doi]
• Machine learning on FPGAs to face the IoT revolutionXiaofan Zhang, Anand Ramachandran, Chuanhao Zhuge, Di He, Wei Zuo, Zuofu Cheng, Kyle Rupnow, Deming Chen. 819-826 [doi]
• Thermal-sensitive design and power optimization for a 3D torus-based optical NoCKang Yao, Yaoyao Ye, Sudeep Pasricha, Jiang Xu. 827-834 [doi]
• VoCaM: Visualization oriented convolutional neural network acceleration on mobile system: Invited paperZhuwei Qin, Zirui Xu, Qide Dong, Yiran Chen, Xiang Chen. 835-840 [doi]
• Offshore oil spill monitoring and detection: Improving risk management for offshore petroleum cyber-physical systems: (Invited paper)Xiaodao Chen, Dongmei Zhang, Yuewei Wang, Lizhe Wang, Albert Y. Zomaya, Shiyan Hu. 841-846 [doi]
• Deep reinforcement learning: Framework, applications, and embedded implementations: Invited paperHongjia Li, Tianshu Wei, Ao Ren, Qi Zhu, Yanzhi Wang. 847-854 [doi]
• Overview of the 2017 CAD contest at ICCAD: Invited paperMyung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake. 855-856 [doi]
• ICCAD-2017 CAD contest in resource-aware patch generationChing-Yi Huang, Chih-Jen Hsu, Chi-An Wu, Kei-Yong Khoo. 857-862 [doi]
• ICCAD-2017 CAD contest in net open location finder with obstacles: Invited paperKai-Shun Hu, Ming-Jen Yang, Yu-Hui Huang, Bing-Yi Wong, Cindy Shen. 863-866 [doi]
• ICCAD-2017 CAD contest in multi-deck standard cell legalization and benchmarksNima Karimpour Darav, Ismail S. Bustany, Andrew A. Kennings, Ravi Mamidi. 867-871 [doi]
• DATC RDF: Robust design flow database: Invited paperJinwook Jung, Pei-Yu Lee, Yan-Shiun Wu, Nima Karimpour Darav, Iris Hui-Ru Jiang, Victor N. Kravets, Laleh Behjat, Yih-Lang Li, Gi-Joon Nam. 872-873 [doi]
• Novel heterogeneous computing platforms and 5G communications for IoT applicationsYuichi Nakamura, Hideyuki Shimonishi, Yuki Kobayashi, Kozo Satoda, Yashuhiro Matsunaga, Dai Kanetomo. 874-879 [doi]
• Edge segmentation: Empowering mobile telemedicine with compressed cellular neural networksXiaowei Xu, Qing Lu, Tianchen Wang, Jinglan Liu, Cheng Zhuo, Xiaobo Sharon Hu, Yiyu Shi. 880-887 [doi]
• CNN-based pattern recognition on nonvolatile IoT platform for smart ultraviolet monitoring: (Invited paper)Jinyang Li, Qingwei Guo, Fang Su, Zhe Yuan, Jinshan Yue, Jingtong Hu, Huazhong Yang, Yongpan Liu. 888-893 [doi]
• Machine learning on FPGAs to face the IoT revolutionXiaofan Zhang, Anand Ramachandran, Chuanhao Zhuge, Di He, Wei Zuo, Zuofu Cheng, Kyle Rupnow, Deming Chen. 894-901 [doi]
• Energy efficient runtime approximate computing on data flow graphsMingze Gao, Gang Qu. 902-907 [doi]
• Deep learning challenges and solutions with Xilinx FPGAsElliott Delaye, Ashish Sirasao, Chaithanya Dudha, Sabya Das. 908-913 [doi]
• FPGA placement and routingShih-Chun Chen, Yao-Wen Chang. 914-921 [doi]
• UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper)Wuxi Li, Meng Li, Jiajun Wang, David Z. Pan. 922-928 [doi]
• Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper)Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu. 929-936 [doi]
• A hybrid approach to cache management in heterogeneous CPU-FPGA platformsLiang Feng, Sharad Sinha, Wei Zhang, Yun Liang. 937-944 [doi]
• An assessment of vulnerability of hardware neural networks to dynamic voltage and temperature variationsXun Jiao, Mulong Luo, Jeng-Hau Lin, Rajesh K. Gupta. 945-950 [doi]
• Dependable integrated clinical system architecture with runtime verificationYu Jiang, Mingzhe Wang, Han Liu, Mohammad Hosseini, Jiaguang Sun. 951-956 [doi]
• Toward safe interoperations in network connected medical cyber-physical systems using open-loop safe protocolsAndrew Y.-Z. Ou, Maryam Rahmaniheris, Yu Jiang, Po-Liang Wu, Lui Sha. 957-963 [doi]
• Model and integrate medical resource availability into verifiably correct executable medical guidelinesChunhui Guo, Zhicheng Fu, Zhenyu Zhang, Shangping Ren, Lui Sha. 964-969 [doi]
• Functional safety methodologies for automotive applicationsAlessandra Nardi, Antonino Armato. 970-975 [doi]
• Impact of circuit-level non-idealities on vision-based autonomous driving systemsHandi Yu, Changhao Yan, Xuan Zeng 0001, Xin Li. 976-983 [doi]
• Timing and security analysis of VANET-based intelligent transportation systems: (Invited paper)Bowen Zheng, Muhammed O. Sayin, Chung-Wei Lin, Shinichi Shiraishi, Qi Zhu. 984-991 [doi]
• ASAP7 predictive design kit development and cell design technology co-optimization: Invited paperVinay Vashishtha, Manoj Vangala, Lawrence T. Clark. 992-998 [doi]
• Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper)Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric. 999-1004 [doi]
• Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper)Kyungwook Chang, Bon Woong Ku, Saurabh Sinha, Sung Kyu Lim. 1005-1010 [doi]
• Cyclist: Accelerating hardware developmentJonathan Bachrach, Albert Magyar, Palmer Dabbelt, Patrick Li, Richard Lin, Krste Asanovic. 1011-1018 [doi]
• Python based framework for HDSLs with an underlying formal semantics: (Invited paper)Keerthikumara Devarajegowda, Johannes Schreiner, Rainer Findenig, Wolfgang Ecker. 1019-1025 [doi]
• Generating FPGA-based image processing accelerators with Hipacc: (Invited paper)Oliver Reiche, M. Akif Ozkan, Richard Membarth, Jürgen Teich, Frank Hannig. 1026-1033 [doi]
• Transportation security in the era of autonomous vehicles: Challenges and practiceSandip Ray. 1034-1038 [doi]
• Security trends and advances in manufacturing systems in the era of industry 4.0Sujit Rokka Chhetri, Nafiul Rashid, Sina Faezi, Mohammad Abdullah Al Faruque. 1039-1046 [doi]
• AEP: An error-bearing neural network accelerator for energy efficiency and model protectionLei Zhao, Youtao Zhang, Jun Yang. 1047-1053 [doi]