Cacheline Utilization-Aware Link Traffic Compression for Modular GPUs - researchr publication authors

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Kishore Punniyamurthy, Shomit Das, Andreas Gerstlauer. Cacheline Utilization-Aware Link Traffic Compression for Modular GPUs. In 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, VLSID 2020, Bangalore, India, January 4-8, 2020. pages 137-142, IEEE, 2020. [doi]

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