Kishore Punniyamurthy, Shomit Das, Andreas Gerstlauer. Cacheline Utilization-Aware Link Traffic Compression for Modular GPUs. In 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, VLSID 2020, Bangalore, India, January 4-8, 2020. pages 137-142, IEEE, 2020. [doi]
@inproceedings{PunniyamurthyDG20,
title = {Cacheline Utilization-Aware Link Traffic Compression for Modular GPUs},
author = {Kishore Punniyamurthy and Shomit Das and Andreas Gerstlauer},
year = {2020},
doi = {10.1109/VLSID49098.2020.00041},
url = {https://doi.org/10.1109/VLSID49098.2020.00041},
researchr = {https://researchr.org/publication/PunniyamurthyDG20},
cites = {0},
citedby = {0},
pages = {137-142},
booktitle = {33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, VLSID 2020, Bangalore, India, January 4-8, 2020},
publisher = {IEEE},
isbn = {978-1-7281-5701-6},
}