An area efficient design methodology for SEU tolerant digital circuits

Sohan Purohit, David Harrington, Martin Margala. An area efficient design methodology for SEU tolerant digital circuits. In International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France. pages 981-984, IEEE, 2010. [doi]

Abstract

Abstract is missing.