Viktor Pus, Juraj Blaho, Jan Korenek. Memory optimizations for packet classification algorithms in FPGA. In Elena Gramatová, Zdenek Kotásek, Andreas Steininger, Heinrich Theodor Vierhaus, Horst Zimmermann, editors, 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010. pages 297-300, IEEE, 2010. [doi]
Abstract is missing.