A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh. A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology. In 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India. pages 192, IEEE Computer Society, 1995. [doi]

This author has not been identified. Look up 'Varna Puvvada' in GoogleThis author has not been identified. Look up 'S. Potla' in GoogleThis author has not been identified. Look up 'S. Tamizh Selvam' in GoogleThis author has not been identified. Look up 'P. R. Suresh' in Google

runs on WebDSL