Sumanta Pyne. An Architectural Support for Reduction of In-rush Current in Systems with Instruction Controlled Power Gating. In Deming Chen, Houman Homayoun, Baris Taskin, editors, Proceedings of the 2018 on Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, May 23-25, 2018. pages 487-490, ACM, 2018. [doi]
@inproceedings{Pyne18-0,
title = {An Architectural Support for Reduction of In-rush Current in Systems with Instruction Controlled Power Gating},
author = {Sumanta Pyne},
year = {2018},
doi = {10.1145/3194554.3194645},
url = {http://doi.acm.org/10.1145/3194554.3194645},
researchr = {https://researchr.org/publication/Pyne18-0},
cites = {0},
citedby = {0},
pages = {487-490},
booktitle = {Proceedings of the 2018 on Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, May 23-25, 2018},
editor = {Deming Chen and Houman Homayoun and Baris Taskin},
publisher = {ACM},
}