A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector - researchr publication authors

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Ki-Hyun Pyun, Dae Hyun Kwon, Woo-Young Choi. A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, South Korea, October 25-28, 2016. pages 327-329, IEEE, 2016. [doi]

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