Ki-Hyun Pyun, Dae Hyun Kwon, Woo-Young Choi. A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, South Korea, October 25-28, 2016. pages 327-329, IEEE, 2016. [doi]
@inproceedings{PyunKC16,
title = {A 3.5/7.0/14-Gb/s multi-rate clock and data recovery circuit with a multi-mode rotational binary phase detector},
author = {Ki-Hyun Pyun and Dae Hyun Kwon and Woo-Young Choi},
year = {2016},
doi = {10.1109/APCCAS.2016.7803966},
url = {http://dx.doi.org/10.1109/APCCAS.2016.7803966},
researchr = {https://researchr.org/publication/PyunKC16},
cites = {0},
citedby = {0},
pages = {327-329},
booktitle = {2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016, Jeju, South Korea, October 25-28, 2016},
publisher = {IEEE},
isbn = {978-1-5090-1570-2},
}