Maoyuan Qin, Xinmu Wang, Baolei Mao, Dejun Mu, Wei Hu 0008. A formal model for proving hardware timing properties and identifying timing channels. Integration, 72:123-133, 2020. [doi]
@article{QinWMMH20,
title = {A formal model for proving hardware timing properties and identifying timing channels},
author = {Maoyuan Qin and Xinmu Wang and Baolei Mao and Dejun Mu and Wei Hu 0008},
year = {2020},
doi = {10.1016/j.vlsi.2020.02.001},
url = {https://doi.org/10.1016/j.vlsi.2020.02.001},
researchr = {https://researchr.org/publication/QinWMMH20},
cites = {0},
citedby = {0},
journal = {Integration},
volume = {72},
pages = {123-133},
}