Mo Qiu, Simin Yu, Yuqiong Wen, Jinhu Lü, Jianbin He, Zhuosheng Lin. Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control. I. J. Bifurcation and Chaos, 27(3):1-15, 2017. [doi]
@article{QiuYWLHL17,
title = {Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control},
author = {Mo Qiu and Simin Yu and Yuqiong Wen and Jinhu Lü and Jianbin He and Zhuosheng Lin},
year = {2017},
doi = {10.1142/S0218127417500407},
url = {https://doi.org/10.1142/S0218127417500407},
researchr = {https://researchr.org/publication/QiuYWLHL17},
cites = {0},
citedby = {0},
journal = {I. J. Bifurcation and Chaos},
volume = {27},
number = {3},
pages = {1-15},
}