Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control - researchr publication

researchr

You are not signed in
Sign in
Sign up

Mo Qiu, Simin Yu, Yuqiong Wen, Jinhu Lü, Jianbin He, Zhuosheng Lin. Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control. I. J. Bifurcation and Chaos, 27(3):1-15, 2017. [doi]

Abstract is missing.

runs on WebDSL