A Testability Enhancement Method for the Memristor Ratioed Logic Circuits

Li Qu, Xiaole Cui, Xiaoxin Cui. A Testability Enhancement Method for the Memristor Ratioed Logic Circuits. In 29th IEEE Asian Test Symposium, ATS 2020, Penang, Malaysia, November 23-26, 2020. pages 1-6, IEEE, 2020. [doi]

Authors

Li Qu

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Xiaole Cui

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Xiaoxin Cui

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