A Testability Enhancement Method for the Memristor Ratioed Logic Circuits

Li Qu, Xiaole Cui, Xiaoxin Cui. A Testability Enhancement Method for the Memristor Ratioed Logic Circuits. In 29th IEEE Asian Test Symposium, ATS 2020, Penang, Malaysia, November 23-26, 2020. pages 1-6, IEEE, 2020. [doi]

@inproceedings{QuCC20,
  title = {A Testability Enhancement Method for the Memristor Ratioed Logic Circuits},
  author = {Li Qu and Xiaole Cui and Xiaoxin Cui},
  year = {2020},
  doi = {10.1109/ATS49688.2020.9301537},
  url = {https://doi.org/10.1109/ATS49688.2020.9301537},
  researchr = {https://researchr.org/publication/QuCC20},
  cites = {0},
  citedby = {0},
  pages = {1-6},
  booktitle = {29th IEEE Asian Test Symposium, ATS 2020, Penang, Malaysia, November 23-26, 2020},
  publisher = {IEEE},
  isbn = {978-1-7281-7467-9},
}