High-level synthesis for large bit-width multipliers on FPGAs: a case study - researchr publication authors

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Gang Quan, James P. Davis, Siddhaveerasharan Devarkal, Duncan A. Buell. High-level synthesis for large bit-width multipliers on FPGAs: a case study. In Petru Eles, Axel Jantsch, Reinaldo A. Bergamaschi, editors, Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005. pages 213-218, ACM, 2005. [doi]

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