Abstract is missing.
- Hardware and software architectures for the CELL processorH. Peter Hofstee, Michael N. Day. 1 [doi]
- Performance and power analysis of computer systemsTrevor N. Mudge. 2 [doi]
- The challenges of embedded system designMike Muller. 3 [doi]
- Future processors: flexible and modularCharlie Johnson, Jeff Welser. 4-6 [doi]
- Future wireless convergence platformsC. John Glossner, Mayan Moudgill, Daniel Iancu, Gary Nacer, Sanjay Jinturkar, Stuart Stanley, Michael Samori, Tanuj Raja, Michael J. Schulte, Stamatis Vassiliadis. 7-12 [doi]
- A core flight software systemJonathan Wilmot. 13-14 [doi]
- Conflict analysis in multiprocess synthesis for optimized system integrationOliver Bringmann, Wolfgang Rosenstiel, Axel Siebenborn. 15-20 [doi]
- A cycle-accurate compilation algorithm for custom pipelined datapathsMehrdad Reshadi, Daniel Gajski. 21-26 [doi]
- Highly flexible multi-mode system synthesisVinu Vijay Kumar, John Lach. 27-32 [doi]
- Energy-efficient address translation for virtual memory support in low-power and real-time embedded processorsXiangrong Zhou, Peter Petrov. 33-38 [doi]
- Automated data cache placement for embedded VLIW ASIPsPaul Morgan, Richard Taylor, Japheth Hossell, George Bruce, Barry O Rourke. 39-44 [doi]
- An efficient direct mapped instruction cache for application-specific embedded systemsChuanjun Zhang. 45-50 [doi]
- Shift buffering technique for automatic code synthesis from synchronous dataflow graphsHyunok Oh, Nikil D. Dutt, Soonhoi Ha. 51-56 [doi]
- Implementation of dynamic streaming Applications on heterogeneous multi-Processor architecturesTomas Henriksson, Jeffrey Kang, Pieter van der Wolf. 57-62 [doi]
- Using minimal minterms to represent programmabilityScott J. Weber, Kurt Keutzer. 63-68 [doi]
- Key research problems in NoC design: a holistic perspectiveÜmit Y. Ogras, Jingcao Hu, Radu Marculescu. 69-74 [doi]
- A unified approach to constrained mapping and routing on network-on-chip architecturesAndreas Hansson, Kees Goossens, Andrei Radulescu. 75-80 [doi]
- Spatial division multiplexing: a novel approach for guaranteed throughput on NoCsAnthony Leroy, Paul Marchal, Adelina Shickova, Francky Catthoor, Frédéric Robert, Diederik Verkest. 81-86 [doi]
- Increasing on-chip memory space utilization for embedded chip multiprocessors through data compressionOzcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin. 87-92 [doi]
- CRAMES: compressed RAM for embedded systemsLei Yang, Robert P. Dick, Haris Lekatsas, Srimat T. Chakradhar. 93-98 [doi]
- Comparing the size of .NET applications with native codeRoberto Costa, Erven Rohou. 99-104 [doi]
- Efficient behavior-driven runtime dynamic voltage scaling policiesFen Xie, Margaret Martonosi, Sharad Malik. 105-110 [doi]
- DVS for buffer-constrained architectures with predictable QoS-energy tradeoffsAlexander Maxiaguine, Samarjit Chakraborty, Lothar Thiele. 111-116 [doi]
- A system-level methodology for fully compensating process variability impact of memory organizations in periodic applicationsAntonis Papanikolaou, F. Lobmaier, Hua Wang, Miguel Miranda, Francky Catthoor. 117-122 [doi]
- What will system level design be when it grows up?Grant Martin, Daniel Gajski, David Goodwin, Patrick Lysaght, Peter Marwedel, Mike Muller, Jeff Welser. 123 [doi]
- The design of a smart imaging core for automotive and consumer applications: a case studyWido Kruijtzer, Winfried Gehrke, Víctor Reyes, Ghiath Alkadi, Thomas Hinz, Jorn Jöchalsky, Bruno Steux. 124-129 [doi]
- Microcoded coprocessor for embedded secure biometric authentication systemsShenglin Yang, Patrick Schaumont, Ingrid Verbauwhede. 130-135 [doi]
- An architectural level design methodology for embedded face detectionVida Kianzad, Sankalita Saha, Jason Schlessman, Gaurav Aggarwal, Shuvra S. Bhattacharyya, Wayne Wolf, Rama Chellappa. 136-141 [doi]
- A power estimation methodology for systemC transaction level modelsNagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan. 142-147 [doi]
- Energy conscious online architecture adaptation for varying latency constraints in sensor network applicationsSankalp Kallakuri, Alex Doboli. 148-153 [doi]
- Aggregating processor free time for energy reductionAviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau. 154-159 [doi]
- Enhanced code density of embedded CISC processors with echo technologyYoufeng Wu, Mauricio Breternitz Jr., Herbert H. J. Hum, Ramesh V. Peri, Jay Pickett. 160-165 [doi]
- Satisfying real-time constraints with custom instructionsPan Yu, Tulika Mitra. 166-171 [doi]
- An integer linear programming approach for identifying instruction-set extensionsKubilay Atasu, Günhan Dündar, Can C. Özturan. 172-177 [doi]
- FIDES: an advanced chip multiprocessor platform for secure next generation mobile terminalsHiroaki Inoue, Akihisa Ikeno, Masaki Kondo, Junji Sakai, Masato Edahiro. 178-183 [doi]
- Power-smart system-on-chip architecture for embedded cryptosystemsRadu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano Gregori. 184-189 [doi]
- Enhancing security through hardware-assisted run-time validation of program data propertiesDivya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha. 190-195 [doi]
- Developing design tools for biological and biomedical applications of micro- and nano-technologyJacob White. 196-200 [doi]
- System-level design automation tools for digital microfluidic biochipsKrishnendu Chakrabarty, Fei Su. 201-206 [doi]
- Blue matter on blue gene/L: massively parallel computation for biomolecular simulationRobert S. Germain, Blake G. Fitch, Aleksandr Rayshubskiy, Maria Eleftheriou, Michael Pitman, Frank Suits, Mark Giampapa, T. J. Christopher Ward. 207-212 [doi]
- High-level synthesis for large bit-width multipliers on FPGAs: a case studyGang Quan, James P. Davis, Siddhaveerasharan Devarkal, Duncan A. Buell. 213-218 [doi]
- Power optimization for universal hash function data path using divide-and-concatenate techniqueBo Yang, Ramesh Karri. 219-224 [doi]
- Efficient performance analysis of asynchronous systems based on periodicityPeggy B. McGee, Steven M. Nowick, Edward G. Coffman Jr.. 225-230 [doi]
- SOMA: a tool for synthesizing and optimizing memory accesses in ASICsGirish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein, Tobias Bjerregaard. 231-236 [doi]
- Memory access optimizations in instruction-set simulatorsMehrdad Reshadi, Prabhat Mishra. 237-242 [doi]
- Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machinesMiljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne. 243-248 [doi]
- Retargetable generation of TLM bus interfaces for MP-SoC platformsAndreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel. 249-254 [doi]
- Automatic network generation for system-on-chip communication designDongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel D. Gajski. 255-260 [doi]
- Service dependency graph: an efficient model for hardware/software interfaces modeling and generation for SoC designAdriano Sarmento, Lobna Kriaa, Arnaud Grasset, Mohamed-Wassim Youssef, Aimen Bouchhima, Frédéric Rousseau, Wander O. Cesário, Ahmed Amine Jerraya. 261-266 [doi]
- A multicast inter-task communication protocol for embedded multiprocessor systemsVíctor Reyes, Tomás Bautista, Gustavo Marrero Callicó, Antonio Núñez, Wido Kruijtzer. 267-272 [doi]
- An automated exploration framework for FPGA-based soft multiprocessor systemsYujia Jin, Nadathur Satish, Kaushik Ravindran, Kurt Keutzer. 273-278 [doi]
- FlexPath NP: a network processor concept with application-driven flexible processing pathsRainer Ohlendorf, Andreas Herkersdorf, Thomas Wild. 279-284 [doi]
- Hardware/software partitioning of software binaries: a case study of H.264 decodeGreg Stitt, Frank Vahid, Gordon McGregor, Brian Einloth. 285-290 [doi]
- Designing real-time H.264 decoders with dataflow architecturesYoungsoo Kim, Suleyman Sair. 291-296 [doi]
- Novel architecture for loop acceleration: a case studySeng Lin Shee, Sri Parameswaran, Newton Cheung. 297-302 [doi]
- Improving superword level parallelism support in modern compilersChristian Tenllado, Luis Piñuel, Manuel Prieto, Francisco Tirado, Francky Catthoor. 303-308 [doi]
- Iterational retiming: maximize iteration-level parallelism for nested loopsChun Xue, Zili Shao, Meilin Liu, Edwin Hsing-Mean Sha. 309-314 [doi]
- Rappit: framework for synthesis of host-assisted scripting engines for adaptive embedded systemsJiwon Hahn, Qiang Xie, Pai H. Chou. 315-320 [doi]
- Dynamic phase analysis for cycle-close trace generationCristiano Pereira, Jeremy Lau, Brad Calder, Rajesh K. Gupta. 321-326 [doi]
- Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptorEdgar L. Romero, Marius Strum, Wang Jiang Chau. 327-332 [doi]
- Grand challenges in embedded systemsJanos Sztipanovits, C. John Glossner, Trevor N. Mudge, Chris Rowen, Alberto L. Sangiovanni-Vincentelli, Wayne Wolf, Feng Zhao. 333 [doi]