Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Bruce Querbach, Rahul Khanna, Sudeep Puligundla, David Blankenbeckler, Joseph Crop, Patrick Yin Chiang. Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC. IEEE Design & Test of Computers, 33(1):59-67, 2016. [doi]

This author has not been identified. Look up 'Bruce Querbach' in GoogleThis author has not been identified. Look up 'Rahul Khanna' in GoogleThis author has not been identified. Look up 'Sudeep Puligundla' in GoogleThis author has not been identified. Look up 'David Blankenbeckler' in GoogleThis author has not been identified. Look up 'Joseph Crop' in GoogleThis author has not been identified. Look up 'Patrick Yin Chiang' in Google

runs on WebDSL