Test Generation in Systolic Architecture for Multiplication Over GF(2 :::m:::)

Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan. Test Generation in Systolic Architecture for Multiplication Over GF(2 :::m:::). IEEE Trans. VLSI Syst., 18(9):1366-1371, 2010. [doi]

@article{RahamanMP10-0,
  title = {Test Generation in Systolic Architecture for Multiplication Over GF(2 :::m:::)},
  author = {Hafizur Rahaman and Jimson Mathew and Dhiraj K. Pradhan},
  year = {2010},
  doi = {10.1109/TVLSI.2009.2023381},
  url = {http://dx.doi.org/10.1109/TVLSI.2009.2023381},
  tags = {architecture, testing},
  researchr = {https://researchr.org/publication/RahamanMP10-0},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. VLSI Syst.},
  volume = {18},
  number = {9},
  pages = {1366-1371},
}