Atul Rahman, Jongeun Lee, Kiyoung Choi. Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array. In Luca Fanucci, Jürgen Teich, editors, 2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016. pages 1393-1398, IEEE, 2016. [doi]
@inproceedings{RahmanLC16,
title = {Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array},
author = {Atul Rahman and Jongeun Lee and Kiyoung Choi},
year = {2016},
url = {http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=7459526},
researchr = {https://researchr.org/publication/RahmanLC16},
cites = {0},
citedby = {0},
pages = {1393-1398},
booktitle = {2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016},
editor = {Luca Fanucci and Jürgen Teich},
publisher = {IEEE},
isbn = {978-3-9815-3707-9},
}