Atul Rahman, Sangyun Oh, Jongeun Lee, Kiyoung Choi. Design space exploration of FPGA accelerators for convolutional neural networks. In David Atienza, Giorgio Di Natale, editors, Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017. pages 1147-1152, IEEE, 2017. [doi]
@inproceedings{RahmanOLC17, title = {Design space exploration of FPGA accelerators for convolutional neural networks}, author = {Atul Rahman and Sangyun Oh and Jongeun Lee and Kiyoung Choi}, year = {2017}, doi = {10.23919/DATE.2017.7927162}, url = {https://doi.org/10.23919/DATE.2017.7927162}, researchr = {https://researchr.org/publication/RahmanOLC17}, cites = {0}, citedby = {0}, pages = {1147-1152}, booktitle = {Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017}, editor = {David Atienza and Giorgio Di Natale}, publisher = {IEEE}, isbn = {978-3-9815370-8-6}, }