Basant Rajan, R. K. Shyamasundar. Modeling VHDL in Multiclock ESTEREL. In 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India. pages 76-83, IEEE Computer Society, 2000. [doi]
@inproceedings{RajanS00,
title = {Modeling VHDL in Multiclock ESTEREL},
author = {Basant Rajan and R. K. Shyamasundar},
year = {2000},
doi = {10.1109/ICVD.2000.812588},
url = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812588},
tags = {meta-model, modeling, Meta-Environment},
researchr = {https://researchr.org/publication/RajanS00},
cites = {0},
citedby = {0},
pages = {76-83},
booktitle = {13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India},
publisher = {IEEE Computer Society},
}