Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops

Antonio Zenteno Ramirez, Guillermo Espinosa, VĂ­ctor H. Champac. Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. IEEE Trans. VLSI Syst., 15(5):572-577, 2007. [doi]

Abstract

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