Athanasios T. Ramkaj, Juan Carlos Pena Ramos, J. M. Marcel Pelgrom, Michiel S. J. Steyaert, Marian Verhelst, Filip Tavernier. A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS. J. Solid-State Circuits, 55(6):1553-1564, 2020. [doi]
Abstract is missing.