Pass Transistor-Based Pull-Up/Pull-Down Insertion Technique for Leakage Power Optimization in CMOS VLSI Circuits

V. Leela Rani, M. Madhavi Latha. Pass Transistor-Based Pull-Up/Pull-Down Insertion Technique for Leakage Power Optimization in CMOS VLSI Circuits. CSSP, 35(11):4139-4152, 2016. [doi]

@article{RaniL16,
  title = {Pass Transistor-Based Pull-Up/Pull-Down Insertion Technique for Leakage Power Optimization in CMOS VLSI Circuits},
  author = {V. Leela Rani and M. Madhavi Latha},
  year = {2016},
  doi = {10.1007/s00034-016-0257-z},
  url = {http://dx.doi.org/10.1007/s00034-016-0257-z},
  researchr = {https://researchr.org/publication/RaniL16},
  cites = {0},
  citedby = {0},
  journal = {CSSP},
  volume = {35},
  number = {11},
  pages = {4139-4152},
}