A Fast Two-level Logic Minimizer

P. Srinivasa Rao, James Jacob. A Fast Two-level Logic Minimizer. In 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India. pages 528-533, IEEE Computer Society, 1998. [doi]

Authors

P. Srinivasa Rao

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James Jacob

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